Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Sept. 7, 2004 to Sept. 10, 2004
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.11
Daniel Matolin , Dresden University of Technology, Germany
J? Schreiter , Dresden University of Technology, Germany
Stefan Getzlaff , Dresden University of Technology, Germany
Ren? Sch? , Dresden University of Technology, Germany
We present a massively parallel VLSI realisation of a pulse-coupled neural network for image segmentation. The network consists of simple integrate-and-fire (IAF) neurons with self-organising local connections. The prototype implementation comprises 64 x 64 neurons with coupling of four nearest neighbours, digital to analog converters, analog memories and a digital readout circuit. The chip has been fabricated in a 0.35μm standard CMOS technology.
D. Matolin, S. Getzlaff, R. Sch? and J. Schreiter, "An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Dresden, Germany, 2004, pp. 51-55.