The Community for Technology Leaders
Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Dresden, Germany
Sept. 7, 2004 to Sept. 10, 2004
ISBN: 0-7695-2080-4
pp: 45-60
Gordon Cichon , Technische Universit?t, Dresden
P. Robelly , Technische Universit?t, Dresden
H. Seidel , Technische Universit?t, Dresden
M. Bronzel , Technische Universit?t, Dresden
Gerhard Fettweis , Technische Universit?t, Dresden
ABSTRACT
This paper presents an adaptation of the list scheduling algorithm to generate code for processors of the Synchronous Transfer Architecture (STA) by applying techniques known from RISC and TTA. The proposed scheduling approach is based on informed, deterministic algorithms that can be implemented run-time efficiently. Although the presented compiler prototype does not generate optimized code, it provides a proof-of-concept of the feasibility of the proposed compiler architecture.
INDEX TERMS
null
CITATION
Gordon Cichon, P. Robelly, H. Seidel, M. Bronzel, Gerhard Fettweis, "Compiler Scheduling for STA-Processors", Parallel Computing in Electrical Engineering, 2004. International Conference on, vol. 00, no. , pp. 45-60, 2004, doi:10.1109/PCEE.2004.20
82 ms
(Ver 3.3 (11022016))