Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Sept. 7, 2004 to Sept. 10, 2004
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.52
Adam Smyk , Polish-Japanese Institute of Information Technology, Warsaw, Poland
Marek Tudruj , Polish-Japanese Institute of Information Technology, Warsaw, Poland; Polish Academy of Sciences, Poland
In this paper, we present a methodology, which enables designing optimal macro data flow graphs that represent computation and communication patterns for the FDTD problem in irregular computational areas. The macro data flow graphs are executed in a MIMD system. Communication is implemented with a Remote Direct Memory Access facility. To obtain minimal communication overheads, the rotating buffers mechanism has been introduced. It is used to control (and synchronize) data flow during execution of fine grain applications with irregular communication. Several methods for data flow graph partitioning and merging are presented. In these methods we take into consideration both computational load balance and minimal communication overhead. Experimental results obtained by simulations are discussed.
M. Tudruj and A. Smyk, "Parallel Implementation of FDTD Computations Based on Macro Data Flow Paradigm," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Dresden, Germany, 2004, pp. 19-24.