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International Conference on Parallel Computing in Electrical Engineering (PARELEC'02) (2002)
Warsaw, Poland
Sept. 22, 2002 to Sept. 25, 2002
ISBN: 0-7695-1730-7
pp: 446
Anna Niedzicka , Polish-Japanese Institute of Information Technology
Image processing hardware found in workstations and server-like computers varies from single processor units to SMP or SMP/SMT configurations and sometimes DMP or massively parallel environments. Image processing can often benefit from introducing parallelism, thus improving owner's return on investment. However, the cost of sharing data between execution resources — and gathering results — can be prohibitively high when speed of simple convolution or arithmetic operation is taken into account. Often a single processor is much faster than available memory bandwidth, making workload decomposition pointless. Non-logarithmic block matching is one of the algorithms that can be challenging even for today's fastest processors, while being useful in high quality compression and picture enhancement or image recognition algorithms. Thanks to high granularity of operations and very few shared resources, careful implementation of block matching algorithm is ideal for parallel execution.

A. Niedzicka, "Computation-Intensive Image Processing Algorithm Parallelization on Multiple Hardware Architectures," International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)(PARELEC), Warsaw, Poland, 2002, pp. 446.
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