International Conference on Parallel Computing in Electrical Engineering (PARELEC'02) (2002)

Warsaw, Poland

Sept. 22, 2002 to Sept. 25, 2002

ISBN: 0-7695-1730-7

pp: 405

Laurence Tianruo Yang , St. Francis Xavier University

ABSTRACT

The PROUD module placement algorithm mainly uses a hierarchical decomposition technique and the solution of sparse linear systems based on a resistive network analogy. It has been shown that the PROUD algorithm can achieve a comparable design of the placement problems for very large circuits with the best placement algorithm based on simulated annealing, but with several order of magnitude faster. The modified PROUD, namely MPROUD algorithm by perturbing the coefficient matrices performs much faster that the original PROUD algorithm. Due to the instability and unguaranteed convergence of MPROUD algorithm, we have proposed a new convergent and numerically stable PROUD, namely Improved PROUD algorithm, denoted as IPROUD with attractive computational costs to solve the module placement problems by making use of the SYMMLQ and MINRES methods based on Lanczos process in [11]. In this paper, we subsequently propose parallel versions of the improved PROUD algorithms. The parallel algorithm is derived such that all inner products and matrix-vector multiplications of a single iteration step are independent. Therefore, the cost of global communication which represents the bottleneck of the parallel performance on parallel distributed memory computers can be significantly reduced, therefore, to obtain another order of magnitude improvement in the runtime without loss of the quality of the layout.

INDEX TERMS

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CITATION

L. T. Yang, "Parallel Efficient Hierarchical Algorithms for Module Placement of Large Chips on Distributed Memory Architectures,"

*International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)(PARELEC)*, Warsaw, Poland, 2002, pp. 405.

doi:10.1109/PCEE.2002.1115310

CITATIONS