International Conference on Parallel Computing in Electrical Engineering (PARELEC'02) (2002)
Sept. 22, 2002 to Sept. 25, 2002
Rainer Schaffer , Dresden University of Technology
Renate Merker , Dresden University of Technology
Francky Catthoor , IMEC and KU Leuven
Upcoming processor generations increasingly provide instructions for sub-word parallelism. Thus, a parallel execution of 2, 4 or 8 instructions (add, sub) or of complex instructions (sum of differences) with an input of 2, 4 or 8 operand pairs becomes possible. The exploitation of sub-word parallelism is still weakly supported by current compilers. To close this gap we present an approach to generate programs for processors with sub-word parallelism. To this end we adapt methods from the design of parallel processor arrays. An algorithm representing a short term analysis filtering is used to illustrate the approach.
F. Catthoor, R. Merker and R. Schaffer, "Systematic Design of Programs with Sub-Word Parallelism," International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)(PARELEC), Warsaw, Poland, 2002, pp. 393.