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International Conference on Parallel Computing in Electrical Engineering (PARELEC'02) (2002)
Warsaw, Poland
Sept. 22, 2002 to Sept. 25, 2002
ISBN: 0-7695-1730-7
pp: 267
A. Katkov , Technical University of Częstochowa
J. Szopa , Technical University of Częstochowa
ABSTRACT
Mathematical and computer simulation of chaotic processes in parallel architecture with speed independent logical units by means of method of chaotic relaxation with delay is considered. This method allows to imitate effectively the fulfillment of chaotic computing process in parallel architecture. It is considered behavior of network consisted from interacting logical units. We use the circuit for defining the end moment of transient processes in logical units. For computer simulation it was chosen the solving the Dirichlet problem for the Laplaces differential equation on a rectangular domain in R<sup>2</sup>. Numerical simulation of solving this problem, with using networks with speed independent logical units are presented.
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CITATION

A. Katkov and J. Szopa, "Chaotic Processing in Parallel Speed Independent Architectures," International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)(PARELEC), Warsaw, Poland, 2002, pp. 267.
doi:10.1109/PCEE.2002.1115264
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