Parallel Computing in Electrical Engineering, 2004. International Conference on (2002)
Sept. 22, 2002 to Sept. 25, 2002
Katalin Pásztor-Varga , E?tv?s Lorand University of Budapest
Let the result of the logic synthesis be a control data flow graph (CDFG) which is prepared to work as a pipeline system. If the restarting period (P) is given the next task is the optimization of the number of the functional elements. To decrease the number of functional elements either one functional element (processor) is allocated to more than one activity or a functional element (processor) is allocated to different activities. In both cases the common time functioning of the activities is examined as the basic data of the allocation algorithm. In this paper an approach of the allocation problem is shown. Here the base of the investigation is an ordered list of the modulo P regarded starting and end points of the transfer scores of the functional elements or activities in the CDFG. So a more effective algorithm is obtained for the normal data flow graph. The algorithm is extended to the graphs containing conditional branches.
High level synthesis, pipeline, control data flow graph, time diagram, allocation
K. Pásztor-Varga, "A Number Theoretical Approach to the Allocation Problem of a Pipelined Dataflow Model," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Warsaw, Poland, 2002, pp. 199.