Parallel Computing in Electrical Engineering, 2004. International Conference on (2002)
Sept. 22, 2002 to Sept. 25, 2002
J. Borkowski , Polish-Japanese Institute of Information Technology
D. Kopański , Polish-Japanese Institute of Information Technology
M. Tudruj , Polish-Japanese Institute of Information Technology
New synchronization mechanism using asynchronous computation activation and cancellation based on state monitoring of a parallel application, are presented. A proposal is given how to integrate the mechanisms with the GRADE graphical parallel program design environment. Necessary enhancements to the GUI along with the semantics and possible applications are presented. Efficient implementation methods for the proposed syncronization are discussed.
J. Borkowski, D. Kopański and M. Tudruj, "Adding Advanced Synchronization to Processes in GRADE," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Warsaw, Poland, 2002, pp. 139.