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International Conference on Parallel Computing in Electrical Engineering (PARELEC'02) (2002)
Warsaw, Poland
Sept. 22, 2002 to Sept. 25, 2002
ISBN: 0-7695-1730-7
pp: 76
Damian Kopanski , Polish-Japanese Institute of Information Technology
Eryk Laskowski , Polish Academy of Sciences
Marek Tudruj , Polish Academy of Sciences
ABSTRACT
<p>The problem of graph modeling of parallel program execution control for the use of symbolic graph simulation facilities is discussed in the paper. This problem has become more important recently, as there is a need for homogenous, symbolic representation of a parallel program and system hardware.</p> <p>The paper presents a method and a new software tool that provide automated extending parallel program graphs by sub-graphs insertions. The inserted sub-graphs represent the execution control of program and the behavior of the system hardware. The tool consists of the graph execution simulator and a special graph specification language based on the XML syntax. They both establish an environment for synthetic parallel program graph execution time evaluation in parallel systems with definable program execution paradigms.</p>
INDEX TERMS
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CITATION

D. Kopanski, E. Laskowski and M. Tudruj, "Modeling Parallel program Execution Control by Directed Graphs with Synchronous Communication," International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)(PARELEC), Warsaw, Poland, 2002, pp. 76.
doi:10.1109/PCEE.2002.1115205
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