International Conference on Parallel Computing in Electrical Engineering (PARELEC'02) (2002)
Sept. 22, 2002 to Sept. 25, 2002
Oleg Maslennikov , Technical University of Koszalin
Juri Shevtshenko , National Technical University of Ukraine
Anatoli Sergyienko , National Technical University of Ukraine
In this paper, the configurable microcontroller array based on the i8051 processor unit (PU) architecture is proposed. The use of well-known PU architecture simplifies the application programming. The designed microcontroller PU core has in 6 times higher instruction implementation speed, and in more than 2.5 times clock frequency than the original microcontroller. The proposed technique of mapping the program into configurable hardware showed the 1.5-2 - fold hardware minimization. It shows an effective way to speedup the implementation of both computing and control intensive algorithms. Proposed array is very useful in such applications, where logic intensive calculations, or high speed byte handling computations are of demand. For example, such applications are homomorphic image processing, pattern recognition, genetic algorithms, neural nets, etc.
A. Sergyienko, O. Maslennikov and J. Shevtshenko, "Configurable Microcontroller Array," International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)(PARELEC), Warsaw, Poland, 2002, pp. 47.