International Conference on Parallel Computing in Electrical Engineering (PARELEC'02) (2002)

Warsaw, Poland

Sept. 22, 2002 to Sept. 25, 2002

ISBN: 0-7695-1730-7

pp: 44

Zbigniew Kokosiński , Cracow University of Technology

ABSTRACT

In this paper a square cellular network for data permutation in a SIMD model is described. It has n<sup>2</sup>/4 2-permuters only, and realizes an arbitrary permutation pattern in two passes. For this network a programming algorithm is provided with O(n) sequential time complexity. Due to its regular cellular structure the square network is suitable for VLSI implementation.

INDEX TERMS

null

CITATION

Z. Kokosiński, "Square Interconnection Network for Data Permutation,"

*International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)(PARELEC)*, Warsaw, Poland, 2002, pp. 44.

doi:10.1109/PCEE.2002.1115195

CITATIONS