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International Conference on Parallel Computing in Electrical Engineering (PARELEC'02) (2002)
Warsaw, Poland
Sept. 22, 2002 to Sept. 25, 2002
ISBN: 0-7695-1730-7
pp: 33
Anna Derezińska , Warsaw University of Technology
Janusz Sosnowski , Warsaw University of Technology
ABSTRACT
The paper deals with the problem of analyzing fault susceptibility of a parallel algorithm designed for a multiprocessor array (MIMD structure). This algorithm realizes quite complex communication protocol in the system. We present an original methodology of the analysis based on the use of software implemented fault injector. The considered algorithm is modeled as a multithreaded application. The experiment set up and results are presented and commented. The performed experiments proved relatively high natural robustness of the analyzed algorithm and showed further possibilities of its improvement.
INDEX TERMS
parallel algorithm, fault injection, multithreaded application, processor array
CITATION

A. Derezińska and J. Sosnowski, "Experimental Checking of Fault Susceptibility in a Parallel Algorithm," International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)(PARELEC), Warsaw, Poland, 2002, pp. 33.
doi:10.1109/PCEE.2002.1115193
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