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International Conference on Parallel Computing in Electrical Engineering (PARELEC'02) (2002)
Warsaw, Poland
Sept. 22, 2002 to Sept. 25, 2002
ISBN: 0-7695-1730-7
pp: 27
Fayez Chayab , RYERSON Polytechnic University
Lev Kirischian , RYERSON Polytechnic University
Lucas Szajek , RYERSON Polytechnic University
This paper presents an approach of automated architecture synthesis for a wide class of parallel multi-mode data-flow embedded computing systems. This approach is based on the method of automated synthesis of multi-mode architectures. This method allows finding the best correspondence between a multi-mode data-flow application (task) and its parallel processing architecture. This method has been implemented in an Architecture-to-Task Optimization System (ATOS) based on a Partially Reconfigurable Computing Platform (PRCP). It was estimated that ATOS could synthesize a complete architecture for an application presented in the form of a Data-Flow Graph within a few seconds including emulation and performance measurements on the PRCP. The proposed approach can dramatically decrease the cost of the R&D design stage and time-to-market for a wide range of parallel multi-mode embedded computing systems.
Parallel architecture, partial reconfiguration, FPGA, automated synthesis, data-flow applications, DFG, optimization

L. Kirischian, L. Szajek and F. Chayab, "Architecture-to-Task Optimization System (ATOS) for Parallel Multi-Mode Data-Flow Architectures on a Base of a Partially Reconfigurable Computing Platform," International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)(PARELEC), Warsaw, Poland, 2002, pp. 27.
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