International Conference on Parallel Computing in Electrical Engineering (PARELEC'00) (2000)
Aug. 27, 2000 to Aug. 30, 2000
Shaowen Song , Wilfrid Laurier University
This paper presents a parallel router and a packet switching mechanism by merging IPv6 and the Asynchronous Transfer Mode (ATM) as the protocol for the Quality of Service (QoS) enabled Internet. The hardware architecture of the parallel router consists of N-number of general-purpose computers each combined with a newly designed inter-node communication unit. This parallel architecture provides the necessary speed required in cell switching for realtime applications. The IPv6 packet and ATM cell co-switching mechanism implemented by the router controlling software preserves the connectionless future for non-realtime applications and provides the Quality of Service (QoS) for realtime applications, through merging the IPv6 and ATM protocols. The IPv6 packet and ATM cell co-routing/switch mechanism is developed for the current parallel router and is presented in this paper along with the parallel hardware architecture.
S. Song, "Multiprocessor Parallel Routing for the Quality of Service Enabled Internet," International Conference on Parallel Computing in Electrical Engineering (PARELEC'00)(PARELEC), Quebec, Canada, 2000, pp. 160.