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International Conference on Parallel Computing in Electrical Engineering (PARELEC'00) (2000)
Quebec, Canada
Aug. 27, 2000 to Aug. 30, 2000
ISBN: 0-7695-0759-X
pp: 155
S. Derrien , IRISA
S. Sur-Kolay , Indian Statistical Institute
ABSTRACT
Reconfigurable Accelerators (RAs) have the potential to provide significant speed-up over many traditional software implementations. However, their effective performance is often limited by their IO capabilities rather than by their computational power. Hence, it became important to consider these constraints when implementing an algorithm on such architecture. In this paper, we propose an IO conscious optimal partitioning strategy for RA based regular array implementations.
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CITATION

S. Rajopadhye, S. Sur-Kolay and S. Derrien, "Optimal Partitioning for FPGA Based Regular Array Implementations," International Conference on Parallel Computing in Electrical Engineering (PARELEC'00)(PARELEC), Quebec, Canada, 2000, pp. 155.
doi:10.1109/PCEE.2000.873620
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