International Conference on Parallel Computing in Electrical Engineering (PARELEC'00) (2000)
Aug. 27, 2000 to Aug. 30, 2000
Anne-Claire Guillou , IRISA
Patrice Quinton , IRISA
Tanguy Risset , IRISA
Daniel Massicotte , Universit? du Qu?bec ? Trois Rivi?res
We present the use of MMAlpha, a tool for the design of parallel VLSI architectures, for the automatic generation of pipelined LMS adaptive filters. Starting from the equations of the applications, MMAlpha allows one to derive a VHDL description of architecture at the register transfer level. We describe the design flow of MMAlpha, which goes through uniform, scheduling, mapping and hardware generation. Results obtained for implementing a delayed LMS algorithm and a look-ahead delayed LMS algorithm on a FPGA Virtex XCV800 chip are shown.
D. Massicotte, T. Risset, A. Guillou and P. Quinton, "Automatic Design of VLSI Pipelined LMS Architectures," International Conference on Parallel Computing in Electrical Engineering (PARELEC'00)(PARELEC), Quebec, Canada, 2000, pp. 144.