A VLSI Systolic Array Architecture for Computation of Third-Order Cumulants for Two-Dimensional Signals
International Conference on Parallel Computing in Electrical Engineering (PARELEC'00) (2000)
Aug. 27, 2000 to Aug. 30, 2000
Ziad H. Mussallam , Advanced Electronics Company
Rana E. Ahmed , Lakehead University
Saleh A. Alshebeili , King Saud University
Cumulants or higher-order statistics have been established as powerful analytical tools in modern signal processing. To estimate cumulants directly from the incoming time-series data in real-time, it is necessary to design a parallel architecture that speeds up the estimation process. This paper describes an efficient VLSI systolic array architecture for computing third-order cumulants for two-dimensional signals. The cumulants estimation algorithm is first reformulated so that any redundancy due to symmetry properties is eliminated. The architecture exploits parallelism, pipelining, and regular cell structures. The architecture, designed with 1.0 ? CMOS process, is capable of operating at a speed of 13 MHz. Performance results, in terms of speedup and efficiency, are presented.
R. E. Ahmed, Z. H. Mussallam and S. A. Alshebeili, "A VLSI Systolic Array Architecture for Computation of Third-Order Cumulants for Two-Dimensional Signals," International Conference on Parallel Computing in Electrical Engineering (PARELEC'00)(PARELEC), Quebec, Canada, 2000, pp. 134.