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International Conference on Parallel Computing in Electrical Engineering (PARELEC'00) (2000)
Quebec, Canada
Aug. 27, 2000 to Aug. 30, 2000
ISBN: 0-7695-0759-X
pp: 100
Lev Kirischian , Ryerson Polytechnic University
ABSTRACT
This paper presents the architecture organization of a task adaptive reconfigurable high-performance computing system for parallel processing of data-flow tasks, The architecture of this reconfigurable system allows flexible distribution of uniform configurable resources (FPGA-based) between tasks, Each task corresponds to a specific Group Processor (GP) adapted for the task requirements. The paper discusses the method of selecting the optimal group processor configuration and mapping group processors on the field of configurable resources. The performance results of the first prototype of the ARGO-parallel computing system are presented.
INDEX TERMS
Reconfigurable architecture: FPGA, Architecture selection graph, Graph arrangement
CITATION

L. Kirischian, "Optimization of Parallel Task Execution on the Adaptive Reconfigurable Group Organized Computing System," International Conference on Parallel Computing in Electrical Engineering (PARELEC'00)(PARELEC), Quebec, Canada, 2000, pp. 100.
doi:10.1109/PCEE.2000.873610
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