International Conference on Parallel Computing in Electrical Engineering (PARELEC'00) (2000)
Aug. 27, 2000 to Aug. 30, 2000
Renate Merker , Dresden University of Technology
In this paper, an approach to high-level synthesis of processor arrays is presented. In particular, we describe methods and tools of the system HLDESA for processor array design, which include resource constraints. Two major groups of resource constraints are considered: implementation constraints such as area and performance constraints to meet desired properties of the array as well as interface constraints such as communication constraints to ensure that the array can be embedded in a given environment. For integrating these two constraint types in the design process of processor arrays, several optimization problems are described, and the method of iterative co-partitioning is presented.
R. Merker, "High-Level Synthesis System (HLDESA) for Processor Arrays," International Conference on Parallel Computing in Electrical Engineering (PARELEC'00)(PARELEC), Quebec, Canada, 2000, pp. 89.