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2013 National Conference on Parallel Computing Technologies (PARCOMPTECH) (2013)
Bangalore, India
Feb. 21, 2013 to Feb. 23, 2013
ISBN: 978-1-4799-1589-7
pp: 1-7
D.C. Kiran , Department of Computer Science and Information Systems, Birla Institute of Technology and Science-Pilani, India
J.P. Misra , Department of Computer Science and Information Systems, Birla Institute of Technology and Science-Pilani, India
D. Yashas , Department of Computer Science and Information Systems, Birla Institute of Technology and Science-Pilani, India
S. Gurunarayanan , Department of Electrical Electronics and Instrumentation, Birla Institute of Technology and Science-Pilani, India
ABSTRACT
Multicore architecture has multiple cores tightly integrated on a single die, with each core having private register files. To maximally utilize the processing power of the architecture, a sequential program is split into small parallel regions to run on different cores. Compile time scheduling and register allocation onto each core can be performed in an integrated manner. For such an integrated approach, an algorithm needs not only to schedule the regions of the program effectively but should also have the ability to detect excessive register demands and to reduce register pressure on the fly. In this paper, an algorithm to perform the integrated instruction scheduling and register allocation without affecting the performance is presented and compared with the normal scheduling approaches.
INDEX TERMS
Control Flow Graph, Multicore, Compiler, Instruction Scheduling, Register Allocation
CITATION
D.C. Kiran, J.P. Misra, D. Yashas, S. Gurunarayanan, "Integrated scheduling and register allocation for multicore architecture", 2013 National Conference on Parallel Computing Technologies (PARCOMPTECH), vol. 00, no. , pp. 1-7, 2013, doi:10.1109/ParCompTech.2013.6621400
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