2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation (2007)

San Diego, California, USA

June 12, 2007 to June 15, 2007

ISBN: 0-7695-2898-8

pp: 211-218

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PADS.2007.4

ABSTRACT

Many partitioning algorithms have been proposed for distributed VLSI simulation. Typically, they make use of a gate level netlist, and attempt to achieve a minimal cut size subject to a load balance constraint. The algorithm executes on a hypergraph which represents the netlist. In this paper we propose a design-driven iterative partitioning algorithm for Verilog based on module instances instead of gates. We do this in order to take advantage of the design hierarchy information contained in the modules and their instances. A Verilog instance represents one vertex in the circuit hypergraph. The vertex can be flattened into multiple vertices in the event that a load balance is not achieved by instance based partitioning. In this case the algorithm flattens the largest instance and moves gates between the partitions in order to improve the load balance. Our experiments show that this partitioning algorithm produces a smaller cutsize than is produced by hmetis on a gate-level netlist. It produces better speedup for the simulation because it takes advantage of the design hierarchy.

INDEX TERMS

Algorithm design and analysis, Partitioning algorithms, Hardware design languages, Iterative algorithms, Clustering algorithms, Circuit simulation, Very large scale integration, Load management, Costs, Computational modeling

CITATION

"A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation",

*2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation*, vol. 00, no. , pp. 211-218, 2007, doi:10.1109/PADS.2007.4