Parallelizing a Sequential Logic Simulator Using an Optimistic Framework Based on a Global Parallel Heap Event Queue: An Experience and Performance Report
Proceedings Fourteenth Workshop on Parallel and Distributed Simulation (2000)
May 28, 2000 to May 31, 2000
Sushil K. Prasad , Georgia State University
Nikhil Junankar , Georgia State University
We have parallelized the Iowa Logic Simulator, a gate-level fine-grained discrete-event simulator, by employing an optimistic algorithm framework based on a global event queue implemented as a parallel heap. The original code and the basic data structures of the serial simulator remained unchanged. Wrapper data structures for the logical processes (gates) and the events are created to allow rollbacks, all the earliest events at each logical processes are stored into the parallel heap, and multiple earliest events are simulated repeatedly by invoking the simulate function of the serial simulator. The parallel heap allowed extraction of hundreds to thousands of earliest events in each queue access. On a bus-based shared-memory multiprocessor, simulation of synthetic circuits with 250,000 gates yielded speedups of 3.3 employing five processors compared to the serial execution time of the Iowa Logic Simulator, and limited the number of rollbacks to within 2,000. The basic steps of parallelization are well defined and general enough to be employable on other discrete-event simulators.
Logic Simulation, Parallelizing Framework, Parallel Heap, Parallel Discrete Event Simulation
S. K. Prasad and N. Junankar, "Parallelizing a Sequential Logic Simulator Using an Optimistic Framework Based on a Global Parallel Heap Event Queue: An Experience and Performance Report," Proceedings Fourteenth Workshop on Parallel and Distributed Simulation(PADS), Bologna, Italy, 2000, pp. 111.