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2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation (2000)
Bologna, Italy
May 28, 2000 to May 31, 2000
ISSN: 1087-4097
ISBN: 0-7695-0677-1
pp: 7
Harold W. Carter , University of Cincinnati
Peter Frey , Cadence Design Systems
Radharamanan Radhakrishnan , University of Cincinnati
Philip A. Wilsey , University of Cincinnati
Circuit simulation has proven to be one of the most important computers aided design (CAD) methods for the analysis and validation of integrated circuit designs. A popular approach to describing circuits for simulation purposes is to use a hardware description language such as VHDL. Similar efforts have also been carried out in the analog domain that has led to tools such as SPICE. However, with the growing trend of hardware designs that contain both analog and digital components, design environments that seamlessly integrate analog and digital circuitry are needed. Simulation of such circuits is however, exacerbated by the higher resource (CPU and memory) demands that arise when analog and digital models are integrated in a mixed-mode (analog and digital) simulation. One solution to this problem is to use PDES algorithms on a distributed platform. However, a synchronization interface between the analog and digital simulation environment is required to achieve integrated mixed-mode simulation. In this paper, we present the issues involved in the construction of synchronization protocols, which support mixed-mode simulation in a distributed simulation environment. The proposed synchronization protocols provide an interface between an optimistic (Time Warp based) discrete-event simulation kernel and any continuous time simulation kernel. Empirical and formal analyses were conducted to ensure correctness and completeness of the protocols and the results of these analyses are presented.
Harold W. Carter, Peter Frey, Radharamanan Radhakrishnan, Philip A. Wilsey, "Parallel Mixed-Technology Simulation", 2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation, vol. 00, no. , pp. 7, 2000, doi:10.1109/PADS.2000.847139
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