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Proceedings 11th Workshop on Parallel and Distributed Simulation (1997)
Lockenhaus, AUSTRIA
June 10, 1997 to June 13, 1997
ISSN: 1087-4097
ISBN: 0-8186-7964-6
pp: 64
Norbert Froëhlich , Institute of Electronic Design Automation Technical University of Munich
Rolf Schlagenhaft , Institute of Electronic Design Automation Technical University of Munich
Josef Fleischmann , Institute of Electronic Design Automation Technical University of Munich
ABSTRACT
For parallel simulation of VLSI circuits on transistor level a sophisticated partitioning of the circuits into subcircuits is crucial. Each net connecting the subcircuits causes additional communication and computation effort. As the slave processors simulating the subcircuits advance synchronously in time, the computation effort for each subcircuit should be approximately the same. In this paper a new approach for partitioning VLSI circuits on transistor level yielding a low number of interconnects between the subcircuits and balanced subcircuit sizes is presented. Simulation of industrial circuits using this partitioning is up to 41% faster than with other known partitioning approaches for parallel analog simulation.
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CITATION
Norbert Froëhlich, Rolf Schlagenhaft, Josef Fleischmann, "A New Approach for Partitioning VLSI Circuits on Transistor Level", Proceedings 11th Workshop on Parallel and Distributed Simulation, vol. 00, no. , pp. 64, 1997, doi:10.1109/PADS.1997.594588
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