Proceedings 11th Workshop on Parallel and Distributed Simulation (1997)
June 10, 1997 to June 13, 1997
Yu-an Chen , University of California at Los Angeles
Vikas Jha , University of California at Los Angeles
Rajive Bagrodia , University of California at Los Angeles
This paper presents the results of an experimental study to evaluate the effectiveness of multiple synchronization protocols and partitioning algorithms in reducing the execution time of switch-level models of VLSI circuits. Specific contributions of this paper include: (i) parallelizing an existing switch-level simulator such that the model can be executed using conservative and optimistic simulation protocols with minor changes, (ii) evaluating effectiveness of several partitioning algorithms for parallel simulation, and (iii) demonstrating speedups with both conservative and optimistic simulation protocols for seven circuits, ranging in size from 3K transistors to about 87K transistors.
V. Jha, Y. Chen and R. Bagrodia, "A Multidimensional Study on the Feasibility of Parallel Switch-Level Circuit Simulation," Proceedings 11th Workshop on Parallel and Distributed Simulation(PADS), Lockenhaus, AUSTRIA, 1997, pp. 46.