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2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation (1997)
Lockenhaus, AUSTRIA
June 10, 1997 to June 13, 1997
ISSN: 1087-4097
ISBN: 0-8186-7964-6
pp: 30
E.M. Rudnick , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
P. Banerjee , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
D. Krishnaswamy , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
ABSTRACT
We propose two new asynchronous parallel algorithms for test set partitioned fault simulation. The algorithms are based on a new two-stage approach to parallelizing fault simulation for sequential VLSI circuits in which the test set is partitioned among the available processors. These algorithms provide the same result as the previous synchronous two stage approach. However, due to the dynamic characteristics of these algorithms and due to the fact that there is very minimal redundant work, they run faster than the previous synchronous approach. A theoretical analysis comparing the various algorithms is also given to provide an insight into these algorithms. The implementations were done in MPI and are therefore portable to many parallel platforms. Results are shown for a shared memory multiprocessor.
INDEX TERMS
circuit analysis computing; asynchronous parallel algorithms; test set partitioned fault simulation; sequential VLSI circuits; synchronous two stage approach; dynamic characteristics; redundant work; MPI; Message Passing Interface; software portability; shared memory multiprocessor; circuit CAD
CITATION
E.M. Rudnick, J.H. Patel, P. Banerjee, D. Krishnaswamy, "Asynchronous parallel algorithms for test set partitioned fault simulation", 2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation, vol. 00, no. , pp. 30, 1997, doi:10.1109/PADS.1997.594583
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