Proceedings of Symposium on Parallel and Distributed Tools (1996)
May 22, 1996 to May 24, 1996
Venkatram Krishnaswamy , Center for Reliable and High Performance Computing, University of Illinois at Urbana-Champaign
Prithviraj Banerjee , Center for Reliable and High Performance Computing, University of Illinois at Urbana-Champaign
One of the methods used to reduce the time spent simulating VHDL designs is by parallelizing the simulation. In this paper, we describe the implementation of an object-oriented Time Warp simulator for VHDL on an actor based environment. The actor model of computation allows the exploitation of fine grained parallelism in a truly asynchronous manner and allows for the overlap of computation with communication. Some preliminary results obtained by simulating a set of multipliers and some ISCAS benchmark circuits are provided. In addition, the importance of placing processes based on circuit partitioning techniques for improving runtimes and scalability is demonstrated. Results are reported on a Sun SPARCServer 1000 and an Intel Paragon.
Parallel Discrete Event Simulation, Time Warp, VHDL
P. Banerjee and V. Krishnaswamy, "Actor Based Parallel VHDL Simulation Using Time Warp," Proceedings of Symposium on Parallel and Distributed Tools(PADS), Philadelphia, PA, 1996, pp. 0135.