2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation (1996)
May 22, 1996 to May 24, 1996
Joerg Keller , Universitaet des Saarlandes
Bernd Rederlechner , Universitaet des Saarlandes
Thomas Rauber , Universitaet des Saarlandes
We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend the critical path analysis technique by partitioning strategies. To incorporate overhead due to the management of data structures, we use a simulation on an ideal parallel machine (PRAM). This simulation can be directly executed on the SB-PRAM prototype, yielding both an implementation and a basis for data structure optimizations. One of the major tools to achieve these is the SB-PRAM's hardware support for parallel prefix operations. Our reimplementation of the PTHOR program on the SB-PRAM yields substantially higher speedups than before.
circuit simulation, conservative simulation, multiprefix operation, parallel random access machine (PRAM), shared memory multiprocessor, speedup estimation
Joerg Keller, Bernd Rederlechner, Thomas Rauber, "Conservative Circuit Simulation on Shared-Memory Multiprocessors", 2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation, vol. 00, no. , pp. 0126, 1996, doi:10.1109/PADS.1996.761570