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Proceedings of Symposium on Parallel and Distributed Tools (1996)
Philadelphia, PA
May 22, 1996 to May 24, 1996
ISBN: 0-8186-7539-X
pp: 0106
K. Hering , Universitaet Leipzig
R. Haupt , Universitaet Leipzig
Th. Villmann , Institut fuer Techno- und Wirtschaftsmathematik
ABSTRACT
The partitioning of complex processor models on the gate and register-transfer level for parallel functional simulation based on the clock-cycle algorithm is considered. We introduce a hierarchical partitioning scheme combining various partitioning algorithms in the frame of a competing strategy. Melting together different partitioning results within one level using superpositions we crossover to a mixture of experts one. This approach is improved applying genetic algorithms. In addition we present two new partitioning algorithms both of them taking cones as fundamental units for building partitions.
INDEX TERMS
Partitioning, VLSI-Design, Logic Simulation, Genetic Algorithms
CITATION
K. Hering, R. Haupt, Th. Villmann, "Hierarchical Strategy of Model Partitioning for VLSI-Design Using an Improved Mixture of Experts Approach", Proceedings of Symposium on Parallel and Distributed Tools, vol. 00, no. , pp. 0106, 1996, doi:10.1109/PADS.1996.761568
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