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2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation (1996)
Philadelphia, PA
May 22, 1996 to May 24, 1996
ISBN: 0-8186-7539-X
pp: 0098
Hong K. Kim , Wright State University
Jack Jean , Wright State University
ABSTRACT
Based on a linear ordering of vertices in a directed graph, a linear-time partitioning algorithm for parallel logic simulation is presented. Unlike most other partitioning algorithms, the proposed algorithm preserves circuit concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the concurrency preserving partitioning (CPP) algorithm can provide better load balancing throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. The algorithm consists of three phases, and three conflicting goals can be separately considered in each phase so to reduce computational complexity. A parallel gate-level circuit simulator is implemented on an Intel Paragon machine to evaluate the performance of the CPP algorithm. The results are compared with two other partitioning algorithms to show that reasonable speedup may be achieved with the algorithm.
INDEX TERMS
Parallel Logic Simulation, Partitioning, Concurrency, Load Balancing, Time Warp
CITATION
Hong K. Kim, Jack Jean, "Concurrency Preserving Partitioning (CPP) for Parallel Logic Simulation", 2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation, vol. 00, no. , pp. 0098, 1996, doi:10.1109/PADS.1996.761567
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