Proceedings 9th Workshop on Parallel and Distributed Simulation (ACM/IEEE) (1995)
Lake Placid, New York
June 14, 1995 to June 16, 1995
R. Bagrodia , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Yu-an Chen , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
V. Jha , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
N. Sonpar , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
This paper presents the results of an experimental study to evaluate the effectiveness of parallel simulation in reducing the execution time of gate-level models of VLSI circuits. Specific contributions of this paper include (i) the design of a gate-level parallel simulator that can be executed, without any changes on both distributed memory and shared memory parallel architectures, (ii) demonstrated speedups with both conservative and optimistic simulation protocols (almost all previous studies on circuit simulation have failed to extract speedups with conservative protocols); in particular we showed that a speedup of about 3 was obtained on 8 processors of a Sparc1000 for conservative algorithms and about 2 for optimistic algorithms for circuits in the ISCAS85 benchmark suite; and (iii) performance comparison between shared memory and distributed memory implementations of the simulator.
VLSI; circuit analysis computing; digital simulation; shared memory systems; parallel programming; logic CAD; logic design; parallel gate-level circuit simulation; shared memory architectures; parallel simulation; execution time; VLSI circuits; gate-level parallel simulator; optimistic simulation protocols; Sparc1000; ISCAS85 benchmark suite
V. Jha, Y. Chen, N. Sonpar and R. Bagrodia, "Parallel gate-level circuit simulation on shared memory architectures," Proceedings 9th Workshop on Parallel and Distributed Simulation (ACM/IEEE)(PADS), Lake Placid, New York, 1995, pp. 170.