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Proceedings 9th Workshop on Parallel and Distributed Simulation (ACM/IEEE) (1995)
Lake Placid, New York
June 14, 1995 to June 16, 1995
ISBN: 0-8186-7120-3
pp: 166
D. Nicol , Dept. of Comput. Sci., Coll. of William & Mary, Williamsburg, VA, USA
E. Carr , Dept. of Comput. Sci., Coll. of William & Mary, Williamsburg, VA, USA
ABSTRACT
This paper reports on the performance of four parallel algorithms for simulating an associative cache operating under the LRU (Least-Recently-Used) replacement policy. Three of the algorithms are implemented on the MasPar MP-2. Another algorithm is a parallelization of an efficient serial algorithm on the Intel Paragon. We assess the strengths and weaknesses of these algorithms as a function of problem size and characteristics, and compare their performance on traces derived from execution of three SPEC92 benchmark programs.
INDEX TERMS
parallel algorithms; cache storage; storage management; virtual machines; content-addressable storage; parallel trace-driven LRU cache simulators; Least-Recently-Used replacement policy; parallel algorithms; associative cache; MasPar MP-2; efficient serial algorithm; Intel Paragon; SPEC92 benchmark programs
CITATION

D. Nicol and E. Carr, "Empirical study of parallel trace-driven LRU cache simulators," Proceedings 9th Workshop on Parallel and Distributed Simulation (ACM/IEEE)(PADS), Lake Placid, New York, 1995, pp. 166.
doi:10.1109/PADS.1995.404304
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