Proceedings 9th Workshop on Parallel and Distributed Simulation (ACM/IEEE) (1995)
Lake Placid, New York
June 14, 1995 to June 16, 1995
D. Nicol , Dept. of Comput. Sci., Coll. of William & Mary, Williamsburg, VA, USA
E. Carr , Dept. of Comput. Sci., Coll. of William & Mary, Williamsburg, VA, USA
This paper reports on the performance of four parallel algorithms for simulating an associative cache operating under the LRU (Least-Recently-Used) replacement policy. Three of the algorithms are implemented on the MasPar MP-2. Another algorithm is a parallelization of an efficient serial algorithm on the Intel Paragon. We assess the strengths and weaknesses of these algorithms as a function of problem size and characteristics, and compare their performance on traces derived from execution of three SPEC92 benchmark programs.
parallel algorithms; cache storage; storage management; virtual machines; content-addressable storage; parallel trace-driven LRU cache simulators; Least-Recently-Used replacement policy; parallel algorithms; associative cache; MasPar MP-2; efficient serial algorithm; Intel Paragon; SPEC92 benchmark programs
D. Nicol and E. Carr, "Empirical study of parallel trace-driven LRU cache simulators," Proceedings 9th Workshop on Parallel and Distributed Simulation (ACM/IEEE)(PADS), Lake Placid, New York, 1995, pp. 166.