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Proceedings 9th Workshop on Parallel and Distributed Simulation (ACM/IEEE) (1995)
Lake Placid, New York
June 14, 1995 to June 16, 1995
ISBN: 0-8186-7120-3
pp: 149
R.M. Fujimoto , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
K.S. Panesar , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
Mechanisms for managing message buffers in Time Warp parallel simulations executing on cache-coherent shared-memory multiprocessors are studied. Two simple buffer management strategies called the sender pool and receiver pool mechanisms are examined with respect to their efficiency, and in particular, their interaction with multiprocessor cache-coherence protocols. Measurements of implementations on a Kendall Square Research KSR-2 machine using both synthetic workloads and benchmark applications demonstrate that sender pools offer significant performance advantages over receiver pools. However, it is also observed that both schemes, especially the sender pool mechanism, are prone to severe performance degradations due to poor locality of reference in large simulations using substantial amounts of message buffer memory. A third strategy called the partitioned buffer pool approach is proposed that exploits the advantages of sender pools, but exhibits much better locality. Measurements of this approach indicate that the partitioned pool mechanism yields substantially better performance than both the sender and receiver pool schemes for large-scale, small-granularity parallel simulation applications. The central conclusions from this study are: (1) buffer management strategies play an important role in determining the overall efficiency of multiprocessor-based parallel simulators, and (2) the partitioned buffer pool organization offers significantly better performance than the sender and receiver pool schemes. These studies demonstrate that poor performance may result if proper attention is not paid to realizing an efficient buffer management mechanism.
time warp simulation; buffer storage; storage management; discrete event simulation; shared memory systems; message passing; multiprocessing programs; buffer management; shared-memory time warp systems; message buffers; cache-coherent shared-memory multiprocessors; sender pool; receiver pool; multiprocessor cache-coherence protocols; Kendall Square Research KSR-2 machine; severe performance degradations; message buffer memory; partitioned buffer pool approach; partitioned pool mechanism; mall-granularity parallel simulation applications; multiprocessor-based parallel simulators

K. Panesar and R. Fujimoto, "Buffer management in shared-memory time warp systems," Proceedings 9th Workshop on Parallel and Distributed Simulation (ACM/IEEE)(PADS), Lake Placid, New York, 1995, pp. 149.
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