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Proceedings 9th Workshop on Parallel and Distributed Simulation (ACM/IEEE) (1995)
Lake Placid, New York
June 14, 1995 to June 16, 1995
ISBN: 0-8186-7120-3
pp: 112
H. Avril , Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
C. Tropper , Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
ABSTRACT
We present, in this paper, a hybrid algorithm which makes use of Time Warp between clusters of LPs and a sequential algorithm within the cluster. Time Warp is, of course, traditionally implemented between individual LPs. The algorithm was implemented in a digital logic simulator, and its performance compared to that of Time Warp. Resting upon this platform we develop a family of three checkpointing algorithms, each of which occupies a different point in the spectrum of possible trade-offs between memory usage and execution time. The algorithms were implemented on several digital logic circuits and their speed, number of states saved and maximal memory consumption were compared to those of Time Warp. One of the algorithms saved between 35 and 50% of the maximal memory consumed by Time Warp (depending upon the number of processors used), while the other two decreased the maximal usage up to 30%. The latter two algorithms exhibited a speed comparable to Time Warp, while the first algorithm was 30-60% slower. These algorithms are also simpler to implement than optimal checkpointing algorithms.
INDEX TERMS
logic CAD; circuit analysis computing; time warp simulation; clustered time warp; logic simulation; hybrid algorithm; sequential algorithm; digital logic simulator; checkpointing algorithms; digital logic circuits; maximal memory consumption
CITATION

H. Avril and C. Tropper, "Clustered time warp and logic simulation," Proceedings 9th Workshop on Parallel and Distributed Simulation (ACM/IEEE)(PADS), Lake Placid, New York, 1995, pp. 112.
doi:10.1109/PADS.1995.404310
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