[Title page i] (PDF)

[Title page iii] (PDF)

[Copyright notice] (PDF)

Table of contents (PDF)

Welcome Message from the General Chair and Program Chair (PDF)

Organizing Committee (PDF)

Program Committee (PDF)

Steering Committee (PDF)

Artifact Evaluation Committee (PDF)

Reviewers (PDF)

Keynotes (PDF)

Sponsors (PDF)

RCU-HTM: Combining RCU with HTM to Implement Highly Efficient Concurrent Binary Search Trees (Abstract)

Redesigning Go’s Built-In Map to Support Concurrent Operations (Abstract)

MultiGraph: Efficient Graph Processing on GPUs (Abstract)

An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech Recognition (Abstract)

DrMP: Mixed Precision-Aware DRAM for High Performance Approximate and Precise Computing (Abstract)

SAM: Optimizing Multithreaded Cores for Speculative Parallelism (Abstract)

Performance Improvement via Always-Abort HTM (Abstract)

DRUT: An Efficient Turbo Boost Solution via Load Balancing in Decoupled Look-Ahead Architecture (Abstract)

Proxy Benchmarks for Emerging Big-Data Workloads (Abstract)

Lightweight Provenance Service for High-Performance Computing (Abstract)

POSTER: Putting the G back into GPU/CPU Systems Research (Abstract)

POSTER: Application-Driven Near-Data Processing for Similarity Search (Abstract)

POSTER: Improving Datacenter Efficiency Through Partitioning-Aware Scheduling (Abstract)

POSTER: The Liberation Day of Nondeterministic Programs (Abstract)

POSTER: Location-Aware Computation Mapping for Manycore Processors (Abstract)

POSTER: BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads (Abstract)

POSTER: DaQueue: A Data-Aware Work-Queue Design for GPGPUs (Abstract)

POSTER: Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls (Abstract)

POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators (Abstract)

POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware (Abstract)

POSTER: Improving NUMA System Efficiency with a Utilization-Based Co-scheduling (Abstract)

POSTER: Bridging the Gap Between Deep Learning and Sparse Matrix Format Selection (Abstract)

POSTER: Cutting the Fat: Speeding Up RBM for Fast Deep Learning Through Generalized Redundancy Elimination (Abstract)

POSTER: Exploiting Approximations for Energy/Quality Tradeoffs in Service-Based Applications (Abstract)

POSTER: Statement Reordering to Alleviate Register Pressure for Stencils on GPUs (Abstract)

POSTER: NUMA-Aware Power Management for Chip Multiprocessors (Abstract)

POSTER: BigBus: A Scalable Optical Interconnect (Abstract)

POSTER: Elastic Reconfiguration for Heterogeneous NoCs with BiNoCHS (Abstract)

Nexus: A New Approach to Replication in Distributed Shared Caches (Abstract)

Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches (Abstract)

Application Clustering Policies to Address System Fairness with Intel’s Cache Allocation Technology (Abstract)

Transparent Dual Memory Compression Architecture (Abstract)

End-to-End Deep Learning of Optimization Heuristics (Abstract)

Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPU (Abstract)

A GPU-Friendly Skiplist Algorithm (Abstract)

Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency (Abstract)

Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries (Abstract)

Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility (Abstract)

Near-Memory Address Translation (Abstract)

Efficient Checkpointing of Loop-Based Codes for Non-volatile Main Memory (Abstract)

SuperGraph-SLP Auto-Vectorization (Abstract)

Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation (Abstract)

A Generalized Framework for Automatic Scripting Language Parallelization (Abstract)

Architecting a Novel Hybrid Cache with Low Energy (Abstract)

Introspective Computing (Abstract)

A DSL for Performance Orchestration (Abstract)

Cache Automaton: Repurposing Caches for Automata Processing (Abstract)

Large Scale Data Clustering Using Memristive k-Median Computation (Abstract)

In-memory Data Flow Processor (Abstract)

Multilayer Compute Resource Management with Robust Control Theory (Abstract)

Author index (PDF)

[Publisher's information] (PDF)