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2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT) (2017)
Portland, Oregon, USA
Sept. 9, 2017 to Sept. 13, 2017
ISBN: 978-1-5090-6764-0
pp: 79-90
ABSTRACT
Several research groups have noted that hardware transactional memory (HTM), even in the case of aborts, can have the side effect of warming up the branch predictor and caches, thereby accelerating subsequent execution. We propose to employ this side effect deliberately, in cases where execution must wait for action in another thread. In doing so, we allow "warm-up" transactions to observe inconsistent state. We must therefore ensure that they never accidentally commit. To that end, we propose that the hardware allow the program to specify, at the start of a transaction, that it should in all cases abort, even if it (accidentally) executes a commit instruction. We discuss several scenarios in which always-abort HTM (AAHTM) can be useful, and present lock and barrier implementations that employ it. We demonstrate the value of these implementations on several real-world applications, obtaining performance improvements of up to 2.5x with almost no programmer effort.
INDEX TERMS
cache storage, microprocessor chips, multiprocessing systems
CITATION

J. Izraelevitz, L. Xiang and M. L. Scott, "Performance Improvement via Always-Abort HTM," 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT), Portland, Oregon, USA, 2017, pp. 79-90.
doi:10.1109/PACT.2017.16
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