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2016 International Conference on Parallel Architecture and Compilation Techniques (PACT) (2016)
Haifa, Israel
Sept. 11, 2016 to Sept. 15, 2016
ISBN: 978-1-5090-5308-7
pp: 453
Roman Kaplan , Technion - Israel Institute of Technology Haifa, Israel
ABSTRACT
In Most contemporary high performance computers are based on von Neumann architecture. It is widely recognized that such architecture suffers from CPU-memory bottleneck. The problem affects both performance and power efficiency of multicore and manycore architectures. With continuation of CPU scaling (driven by Moore's law and parallelization), the von Neumann bottleneck problem will become even more acute.
INDEX TERMS
Computer architecture, Random access memory, Three-dimensional displays, Performance evaluation, Home appliances, Heuristic algorithms, Algorithm design and analysis
CITATION
Roman Kaplan, "Student research poster - from processing-in-Memory to Processing-in-Storage", 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT), vol. 00, no. , pp. 453, 2016, doi:10.1145/2967938.2971463
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