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2016 International Conference on Parallel Architecture and Compilation Techniques (PACT) (2016)
Haifa, Israel
Sept. 11, 2016 to Sept. 15, 2016
ISBN: 978-1-5090-5308-7
pp: 447-448
Milan Stanic , Barcelona Supercomputing Center, Spain
Oscar Palomar , University of Manchester, UK
Timothy Hayes , Barcelona Supercomputing Center, Spain
Ivan Ratkovic , Barcelona Supercomputing Center, Spain
Osman Unsal , Barcelona Supercomputing Center, Spain
Adrian Cristal , Barcelona Supercomputing Center, Spain
Mateo Valero , Barcelona Supercomputing Center, Spain
ABSTRACT
In the low-end mobile processor market, power, energy and area budgets are significantly lower than in other markets (e.g. servers or high-end mobile markets). It has been shown that vector processors are a highly energy-efficient way to increase performance; however adding support for them incurs area and power overheads that would not be acceptable for low-end mobile processors. In this work, we propose an integrated vector-scalar design for the ARM architecture that mostly reuses scalar hardware to support the execution of vector instructions. The key element of the design is our proposed block-based model of execution that groups vector computational instructions together to execute them in a coordinated manner.
INDEX TERMS
Computational modeling, Vector processors, Computer architecture, Mobile communication, Integrated design, Registers,mobile, vector processors, low-power, energy efficiency
CITATION
Milan Stanic, Oscar Palomar, Timothy Hayes, Ivan Ratkovic, Osman Unsal, Adrian Cristal, Mateo Valero, "POSTER: An integrated vector-scalar design on an in-order ARM core", 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT), vol. 00, no. , pp. 447-448, 2016, doi:10.1145/2967938.2974057
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