The Community for Technology Leaders
2016 International Conference on Parallel Architecture and Compilation Techniques (PACT) (2016)
Haifa, Israel
Sept. 11, 2016 to Sept. 15, 2016
ISBN: 978-1-5090-5308-7
pp: 433-434
Alberto Ros , Universidad de Murcia, Spain
Carl Leonardsson , Uppsala Universitet, Sweden
Christos Sakalis , Uppsala Universitet, Sweden
Stefanos Kaxiras , Uppsala Universitet, Sweden
Cache coherence protocols based on self-invalidation allow simpler hardware implementation compared to traditional write-invalidation protocols, by relying on data-race-free semantics and applying self-invalidation and self-downgrade on synchronization points. This work examines how self-invalidation and self-downgrade are performed in relation to atomicity and ordering and shows that they do not need to be applied conservatively, as so far implemented. Our key observation is that, often, critical sections which are not ordered in time, are intended to provide only atomicity but not thread synchronization.
Synchronization, Coherence, Instruction sets, Semantics, Protocols, Computer architecture, Proposals,atomicity, Cache coherence, memory consistency, self-invalidation, critical sections
Alberto Ros, Carl Leonardsson, Christos Sakalis, Stefanos Kaxiras, "POSTER: Efficient self-invalidation/self-downgrade for critical sections with relaxed semantics", 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT), vol. 00, no. , pp. 433-434, 2016, doi:10.1145/2967938.2974050
105 ms
(Ver 3.3 (11022016))