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2016 International Conference on Parallel Architecture and Compilation Techniques (PACT) (2016)
Haifa, Israel
Sept. 11, 2016 to Sept. 15, 2016
ISBN: 978-1-5090-5308-7
pp: 421-422
Florian Haas , Department of Computer Science, University of Augsburg, Germany
Sebastian Weis , Department of Computer Science, University of Augsburg, Germany
Theo Ungerer , Department of Computer Science, University of Augsburg, Germany
Gilles Pokam , Intel Corporation, Santa Clara, United States of America
Youfeng Wu , Intel Corporation, Santa Clara, United States of America
ABSTRACT
Software-based fault-tolerance mechanisms can increase the reliability of multi-core CPUs while being cheaper and more flexible than hardware solutions like lockstep architectures. However, checkpoint creation, error detection and correction entail high performance overhead if implemented in software. We propose a software/hardware hybrid approach, which leverages Intel's hardware transactional memory (TSX) to support implicit checkpoint creation and fast rollback. Hardware enhancements are proposed and evaluated, leading to a resulting performance overhead of 19% on average.
INDEX TERMS
Hardware, Instruments, Fault tolerance, Fault tolerant systems, Bars, Multicore processing
CITATION
Florian Haas, Sebastian Weis, Theo Ungerer, Gilles Pokam, Youfeng Wu, "POSTER: Fault-tolerant execution on COTS multi-core processors with hardware transactional memory support", 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT), vol. 00, no. , pp. 421-422, 2016, doi:10.1145/2967938.2974051
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