2016 International Conference on Parallel Architecture and Compilation Techniques (PACT) (2016)
Sept. 11, 2016 to Sept. 15, 2016
Fady Ghanim , Electrical and Computer Engineering Department, University of Maryland, College Park, 20742, USA
Rajeev Barua , Electrical and Computer Engineering Department, University of Maryland, College Park, 20742, USA
Uzi Vishkin , Electrical and Computer Engineering Department, University of Maryland, College Park, 20742, USA
Large performance growth for processors requires exploitation of hardware parallelism, which, itself, requires parallelism in software. In spite of massive efforts, automatic parallelization of serial programs has had limited success mostly for regular programs with affine accesses, but not for many applications including irregular ones. It appears that the bare minimum that the programmer needs to spell out is which operations can be executed in parallel. However, parallel programming today requires so much more. The programmer is expected to partition a task into subtasks (often threads) so as to meet multiple constraints and objectives, involving data and computation partitioning, locality, synchronization, race conditions, limiting and hiding communication latencies. It is no wonder that this makes parallel programming hard, drastically reducing programmer's productivity and performance gains hence reducing adoption by programmers and their employers. Suppose, however, that the effort of the programmer is reduced to merely stating operations that can be executed in parallel, the ‘work-depth’ bare minimum abstraction developed for PRAM (the lead theory of parallel algorithms). What performance penalty should this incur? Perhaps surprisingly, the upshot of our work is that this can be done with no performance penalty relative to hand-optimized multi-threaded code.
Ice, Phase change random access memory, Parallel programming, Parallel processing, Instruction sets, Hardware,PRAM, Parallel Programming Languages, ease of programming, ICE, Parallel Algorithms
Fady Ghanim, Rajeev Barua, Uzi Vishkin, "Poster: Easy PRAM-based high-performance parallel programming with ICE", 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT), vol. 00, no. , pp. 419-420, 2016, doi:10.1145/2967938.2974053