2016 International Conference on Parallel Architecture and Compilation Techniques (PACT) (2016)
Sept. 11, 2016 to Sept. 15, 2016
Nitin Chugh , International Institute of Information Technology, Hyderabad 500032 India
Vinay Vasista , Dept of CSA, Indian Institute of Science, Bengaluru 560012 India
Suresh Purini , International Institute of Information Technology, Hyderabad 500032 India
Uday Bondhugula , Dept of CSA, Indian Institute of Science, Bengaluru 560012 India
This paper describes an automatic approach to accelerate image processing pipelines using FPGAs. An image processing pipeline can be viewed as a graph of interconnected stages that processes images successively. Each stage typically performs a point-wise, stencil, or other more complex operations on image pixels. Recent efforts have led to the development of domain-specific languages (DSL) and optimization frameworks for image processing pipelines. In this paper, we develop an approach to map image processing pipelines expressed in the PolyMage DSL to efficient parallel FPGA designs. Our approach exploits reuse and available memory bandwidth (or chip resources) maximally. When compared to Darkroom, a state-of-the-art approach to compile high-level DSL to FPGAs, our approach (a) leads to designs that deliver significantly higher throughput, and (b) supports a greater variety of filters. Furthermore, the designs we generate obtain an improvement even over pre-optimized FPGA implementations provided by vendor libraries for some of the benchmarks.
Field programmable gate arrays, Pipelines, DSL, Image processing, Optimization, Pipeline processing
N. Chugh, V. Vasista, S. Purini and U. Bondhugula, "A DSL compiler for accelerating image processing pipelines on FPGAs," 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT), Haifa, Israel, 2016, pp. 327-338.