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2016 International Conference on Parallel Architecture and Compilation Techniques (PACT) (2016)
Haifa, Israel
Sept. 11, 2016 to Sept. 15, 2016
ISBN: 978-1-5090-5308-7
pp: 275-286
Paul Caheny , Barcelona Supercomputing Center, Spain
Marc Casas , Barcelona Supercomputing Center, Spain
Miquel Moreto , Barcelona Supercomputing Center, Spain
Herve Gloaguen , Bull Atos Technologies, Les Clayes-sous-Bois, France
Maxime Saintes , Bull Atos Technologies, Les Clayes-sous-Bois, France
Eduard Ayguade , Barcelona Supercomputing Center, Spain
Jesus Labarta , Barcelona Supercomputing Center, Spain
Mateo Valero , Barcelona Supercomputing Center, Spain
ABSTRACT
Cache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the flat memory address space they offer considerably improves programmability. However, ccNUMA architectures require sophisticated and expensive cache coherence protocols to enforce correctness during parallel executions, which trigger a significant amount of on- and off-chip traffic in the system. This paper analyses how coherence traffic may be best constrained in a large, real ccNUMA platform through the use of a joint hardware/software approach. For several benchmarks, we study coherence traffic in detail under the influence of an added hierarchical cache layer in the directory protocol combined with runtime managed NUMA-aware scheduling and data allocation techniques to make most efficient use of the added hardware. The effectiveness of this joint approach is demonstrated by speedups of 1.23× to 2.54× and coherence traffic reductions between 44% and 77% in comparison to NUMA-oblivious scheduling and data allocation. Furthermore, we show that the NUMA-aware techniques we employ at the runtime level are crucial to ensure the added hierarchical layer in the directory coherence protocol does not introduce significant coherence traffic to the system.
INDEX TERMS
Coherence, Switched-mode power supply, Memory management, Runtime, Resource management, Protocols
CITATION
Paul Caheny, Marc Casas, Miquel Moreto, Herve Gloaguen, Maxime Saintes, Eduard Ayguade, Jesus Labarta, Mateo Valero, "Reducing cache coherence traffic with hierarchical directory cache and NUMA-aware runtime scheduling", 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT), vol. 00, no. , pp. 275-286, 2016, doi:10.1145/2967938.2967962
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