The Community for Technology Leaders
2014 23rd International Conference on Parallel Architecture and Compilation (PACT) (2014)
Edmonton, Canada
Aug. 23, 2014 to Aug. 27, 2014
ISBN: 978-1-5090-6607-0
pp: 507-508
Sudharsan Jagathrakshakan , Indian Institute of Technology, Madras
Venkata Kalyan Tavva , Indian Institute of Technology, Madras
Madhu Mutyam , Indian Institute of Technology, Madras
ABSTRACT
In modern day systems, main memory contributes significantly to the overall power consumption. One of the features provided by JEDEC DDR3 standard onwards is Burst Chop (BC) through which the Burst Length of the data access commands (CAS) can be configured. This work aims to improve the energy efficiency of the DRAM memory by exploiting the existing BC features for half writes (writes in which either the first half or second half of the cache block is dirty). We propose to change the mapping of words of a cache block to the DRAM devices in order to reduce the number of devices involved in half writes. With our new mapping, we achieve average memory power savings of 3.27% with negligible impact on performance.
INDEX TERMS
Random access memory, Hardware, Memory management, Power demand, Performance evaluation, Data transfer, Benchmark testing
CITATION
Sudharsan Jagathrakshakan, Venkata Kalyan Tavva, Madhu Mutyam, "Data remapping for an energy efficient burst chop in DRAM memory systems", 2014 23rd International Conference on Parallel Architecture and Compilation (PACT), vol. 00, no. , pp. 507-508, 2014, doi:10.1145/2628071.2671424
82 ms
(Ver 3.3 (11022016))