2014 23rd International Conference on Parallel Architecture and Compilation (PACT) (2014)
Aug. 23, 2014 to Aug. 27, 2014
Bradley Thwaites , Georgia Institute of Technology
Gennady Pekhimenko , Carnegie Mellon University
Hadi Esmaeilzadeh , Georgia Institute of Technology
Amir Yazdanbakhsh , Georgia Institute of Technology
Jongse Park , Georgia Institute of Technology
Girish Mururu , Georgia Institute of Technology
Onur Mutlu , Carnegie Mellon University
Todd Mowry , Carnegie Mellon University
This paper demonstrates how to utilize the inherent error resilience of a wide range of applications to mitigate the memory wall — the discrepancy between core and memory speed. We define a new microarchitecturally-triggered approximation technique called rollback-free value prediction. This technique predicts the value of safe-to-approximate loads when they miss in the cache without tracking mispredictions or requiring costly recovery from misspeculations. This technique mitigates the memory wall by allowing the core to continue computation without stalling for long-latency memory accesses. Our detailed study of the quality trade-offs shows that with a modern out-of-order processor, average 8% (up to 19%) performance improvement is possible with 0.8% (up to 1.8%) average quality loss on an approximable subset of SPEC CPU 2000/2006.
Microarchitecture, Degradation, Semantics, Computer architecture, Runtime, Safety, Software
B. Thwaites et al., "Rollback-free value prediction with approximate loads," 2014 23rd International Conference on Parallel Architecture and Compilation (PACT), Edmonton, Canada, 2014, pp. 493-494.