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2014 23rd International Conference on Parallel Architecture and Compilation (PACT) (2014)
Edmonton, Canada
Aug. 23, 2014 to Aug. 27, 2014
ISBN: 978-1-5090-6607-0
pp: 491-492
Sudarshan Srinivasan , ECE Department, University of Massachusetts Amherst, MA, USA
Nithesh Kurella , ECE Department, University of Massachusetts Amherst, MA, USA
Israel Koren , ECE Department, University of Massachusetts Amherst, MA, USA
Sandip Kundu , ECE Department, University of Massachusetts Amherst, MA, USA
Rance Rodrigues , NVIDIA Beaverton, Oregon, USA
ABSTRACT
Asymmetric multicore processors (AMPs) consist of cores executing the same ISA, but differing in microarchitectural resources, performance, and power consumption. As the computational bottleneck of a workload shifts from one resource to the next, during its course of execution, reassigning it to the core where it runs most efficiently can improve the overall energy efficiency. Simulation studies show that the performance bottlenecks can shift frequently, often within a few thousands cycles. With frequent core hooping, the overhead of thread migration becomes significant. To mitigate this overhead, we propose a morphable core that can assume one of four possible configurations to address the dominant performance bottlenecks, while retaining the same cache and registers. This way the architectural state remains intact while the morphable core is reconfigured in resources and frequency. We then implement a runtime scheme to decide the best configuration to run on and switch configuration as necessary. Simulation results indicate that on the average, the proposed scheme results in performance/watt improvement of 41%.
INDEX TERMS
Multicore processing, Switches, Out of order, Radiation detectors, Benchmark testing,Core Morphing, Asymmetric multi-core processors, Hardware Performance Counters
CITATION
Sudarshan Srinivasan, Nithesh Kurella, Israel Koren, Sandip Kundu, Rance Rodrigues, "A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency", 2014 23rd International Conference on Parallel Architecture and Compilation (PACT), vol. 00, no. , pp. 491-492, 2014, doi:10.1145/2628071.2628124
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