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2014 23rd International Conference on Parallel Architecture and Compilation (PACT) (2014)
Edmonton, Canada
Aug. 23, 2014 to Aug. 27, 2014
ISBN: 978-1-5090-6607-0
pp: 485-486
Xiang Pan , Computer Science and Engineering, The Ohio State University
Radu Teodorescu , Computer Science and Engineering, The Ohio State University
ABSTRACT
Near-threshold computing is gaining traction as an energy-efficient solution for power-constrained systems. This paper proposes a novel near-threshold chip multiprocessor design that uses non-volatile spin-transfer torque random access memory (STT-RAM) technology to implement all on-chip caches. This technology has several advantages over SRAM that are particularly useful in near-threshold designs. Primarily, STT-RAM has very low leakage, saving a substantial fraction of the power consumed by near-threshold chips. In addition, the STT-RAM components run at a higher supply voltage to speed up write operations. This has the effect of making cache reads very fast to the point where L1 caches can be shared by several cores, improving performance. Overall, the proposed design saves 11–33% energy compared to an SRAM-based near-threshold system.
INDEX TERMS
Random access memory, Power demand, Clocks, Nonvolatile memory, System-on-chip, Computer science, Torque
CITATION
Xiang Pan, Radu Teodorescu, "Using STT-RAM to enable energy-efficient near-threshold chip multiprocessors", 2014 23rd International Conference on Parallel Architecture and Compilation (PACT), vol. 00, no. , pp. 485-486, 2014, doi:10.1145/2628071.2628132
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