2014 23rd International Conference on Parallel Architecture and Compilation (PACT) (2014)
Aug. 23, 2014 to Aug. 27, 2014
Deepak Majeti , Rice University
Kuldeep S. Meel , Rice University
Rajkishore Barik , Intel Labs
Vivek Sarkar , Rice University
Data layouts play a crucial role in determining the performance of a given application running on a given architecture. Existing parallel programming frameworks for both multicore and heterogeneous systems leave the onus of selecting a data layout to the programmer. Therefore, shifting the burden of data layout selection to optimizing compilers can greatly enhance programmer productivity and application performance. In this work, we introduce ADHA: a two-level hierarchal formulation of the data layout problem for modern heterogeneous architectures. We have created a reference implementation of ADHA in the Heterogeneous Habanero-C (H2C) parallel programming system. ADHA shows significant performance benefits of up to 6.92× compared to manually specified layouts for two benchmark programs running on a CPU+GPU heterogeneous platform.
Layout, Graphics processing units, Benchmark testing, Kernel, Computer architecture, Biomedical imaging
D. Majeti, K. S. Meel, R. Barik and V. Sarkar, "ADHA: Automatic data layout framework for heterogeneous architectures," 2014 23rd International Conference on Parallel Architecture and Compilation (PACT), Edmonton, Canada, 2014, pp. 479-480.