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2014 23rd International Conference on Parallel Architecture and Compilation (PACT) (2014)
Edmonton, Canada
Aug. 23, 2014 to Aug. 27, 2014
ISBN: 978-1-5090-6607-0
pp: 477-478
Yulong Luo , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Guangming Tan , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
ABSTRACT
Stencil computation is a performance critical kernel used in scientific and engineering applications. We define a term of locality of computation to guide stencil optimization by either architecture or compiler. Being analogous to locality of reference, computational behavior is also classified into spatial locality and temporal locality. This paper develops equivalent computation elimination (ECE) approach in multi-level loop for exploiting temporal locality of computation. The strength of ECE lies on an intermediate-based searching algorithm to eliminate inter-iteration computational redundancies of all possible combination and a multiple dimensions replacement algorithm to replace redundant computation across loops of multiple dimensions. We implemented ECE in ROSE compiler infrastructure. The experiment shows that ECE improves performance by 20% on average due to the consciousness of temporal locality.
INDEX TERMS
Redundancy, Optimization, Computer architecture, Kernel, Registers, Computers, Computer languages,ROSE, Stencil, locality of computation, equivalent computation elimination
CITATION
Yulong Luo, Guangming Tan, "Optimizing stencil code via locality of computation", 2014 23rd International Conference on Parallel Architecture and Compilation (PACT), vol. 00, no. , pp. 477-478, 2014, doi:10.1145/2628071.2628121
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